1. Field of the Invention
The present invention relates to an alignment key structure in a semiconductor device and to a method of manufacturing the same. More particularly, the present invention relates to an alignment key structure employed in a wire bonding process for electrically connecting a bonding pad of a semiconductor device to lead of a lead frame using a conductive line, and to a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device is generally manufactured by the following processes (i) a fabrication (FAB) process that forms electrical circuits on a semiconductor substrate such as a silicon wafer, (ii) an electrical die sorting (EDS) process that tests electrical characteristics of the semiconductor device and (iii) a packaging process that wraps the individual semiconductor device up.
In particular, a wire bonding process as part of the above-mentioned packaging process is performed for connecting a bonding pad formed on the semiconductor device with lead of a lead frame, using a conductive line such as a gold line.
FIG. 1 is a plan view showing upper structures of a conventional semiconductor device. FIG. 2 is a cross sectional view showing the upper structures of the conventional semiconductor device illustrated in FIG. 1.
Referring to FIGS. 1 and 2, semiconductor structures 102 are formed on a semiconductor substrate such as a silicon wafer. The semiconductor structures 102 have integrated circuits (not shown) that include a transistor, a capacitor, and a pad. A first insulating interlayer 112 and a second insulating interlayer 124 are formed on the semiconductor structures 102. The first insulating interlayer 112 includes a plurality of first metal wirings electrically contacted to the integrated circuits. The second insulating interlayer 124 includes a plurality of second metal wirings and a bonding pad 122.
Moreover, a passivation layer pattern 130 is formed on the second insulating interlayer 124 to protect the above semiconductor devices. In addition, a first opening 132 and a second opening 134 are formed in the passivation layer pattern 130. The first opening 132 serves as an alignment key in a wire bonding process. The second opening 134 exposes the bonding pad 122. The first opening 132 and the second opening 134 are connected with each other as shown in FIG. 2. Alternatively, the first opening 132 and the second opening 134 may be formed independently.
The first opening 132 typically has a clamp shape and exposes second metal wirings 120 adjacent to the bonding pad 122. The first opening 132 and the second opening 134 are formed by an etching process using an etchant such as plasma. However, the second metal wirings 120 can be subject to etch damage during the etching process. The consequences of such etch damage to the second metal wirings 120 will be described below.
Particularly, the second metal wirings 120 include a plurality of signal lines, power lines, and ground lines. Thus, when the signal lines are exposed through the first opening 132, signal noise may occur as a result of etch damage to the second metal wirings. The signal noise in turn may then deteriorate the reliability of the semiconductor device. In addition, since the signal lines have relatively narrower widths than the widths of the power lines or the ground lines, a short or failure of the signal lines may also occur during the etching process. Furthermore, when etch damage occurs to the second wirings 120, plasma etch damage may also occur in the first metal wirings 110 below the first opening 132 as well, which may in turn lead to further signal noise.
Accordingly there is a need in the art for an alignment key structure in a semiconductor device and a method of forming the same which prevents etching damage from occurring to metal wirings in a process for manufacturing a semiconductor device.